The semiconductor industry is continuously moving toward the fabrication of smaller and more complex microelectronic components with higher performance. Memory cells are an important part of many microelectronic components, and smaller and more reliable memory cells are desirable. One type of memory cell uses flash memory that is non-volatile and re-writable. Non-volatile memory retains stored information even when the memory cell is de-powered, and stored information can be changed when a memory cell is re-writable. Some memory cells for flash memory store information by either charging or draining an electrically isolated component, such as a floating gate, and the information is recalled by determining if the isolated component is charged or not. Floating gate memory cells are typically provided with associated control gates and select gates that are utilized in the storage, retrieval, and erasing of memory on the floating gate.
In some embodiments, floating gate memory cells are formed in pairs, with a central plug initially formed between a first and second floating gate memory cell. A control gate is positioned over the floating gate for the first and second memory cells, and a floating barrier is positioned between the control gate and the floating gate. The floating barrier is a dielectric that electrically separates the control gate from the floating gate. In the manufacturing process, a cap is positioned over the control gate so the floating gate, floating barrier, control gate, and cap form a “stack” of components. The select gate is formed adjacent to the stack and on the opposite side of the stack from the central plug. The central plug and the cap are removed during the manufacturing process. Removal of the cap often results in undesirable partial etching of the floating barrier positioned between the floating gate and the control gate because similar materials are often used in the cap and the floating barrier. Partial etching of the floating barrier can change the voltage or current needed to read or write from the memory cell. The floating barrier is etched to varying degrees for different memory cells, so the operation of a memory bank can be compromised because different memory cells require different voltages or currents. A typical memory bank does not provide individually customized voltages or currents for operation of individual memory cells, so some of the memory cells will not function properly.
Electrical connects present another challenge for floating gate memory cells. In a typical floating gate memory cell, the control gate and the select gate each extend to about the same height. The control gate and the select gate are separated by a relatively thin select gate dielectric. Silicides are formed on the surface of many electronic components to improve the electrical connection with a contact, but the surface of the electronic component expands and grows during the silicide formation. Silicides formed on the control gate and the select gate often grow to the point that they make an electrical connection over the top of the select gate dielectric, so the memory cell is shorted and does not function. Therefore, many memory cells are produced without surface silicides. The lack of a silicide on the surface of the select gate and the control gate increases electrical resistance at the contact, and thereby reduces the performance of the memory cell.
Accordingly, it is desirable to provide floating gate memory cells with silicides on the select gate and the control gate, and methods for manufacturing the same. In addition, it is desirable to provide floating gate memory cells with consistent floating barriers between the floating gate and the control gate, and methods of manufacturing the same. Furthermore, other desirable features and characteristics of the present embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.